The invention relates to frequency synthesis, and more particularly to a fast-locking scheme for use in a frequency synthesizer.
The rapid growth of cellular communications systems has motivated an increasing demand for high performance integrated radio frequency (RF) components. One of the most important building blocks of these systems is the local oscillator (LO). In modern RF transceivers, the oscillators are usually embedded in a synthesizer environment so as to achieve a precise definition of the output frequency. Phase-locked loop (PLL) techniques have been widely used in frequency synthesis to meet the stringent requirements of wireless standards, because under locked condition the output frequency of a PLL bears an exact relationship with the input frequency.
A PLL-based synthesis technique offers high integration, low power dissipation, small chip area, high reliability, and predictable performance. There are a wide variety of frequency synthesizers disclosed in United States patents including U.S. Pat. No. 6,150,891 for example. It is known that the synthesizer requires a finite time to establish a new frequency when a communications system intends a change in the channel. The performance of communications systems is critically dependent on the lock time of frequency synthesizers. The lock time is an indication of how fast the new frequency is stabilized. This parameter is especially important in fast frequency-hopped systems.